Multi Objective Analysis of NCL Threshold Gates with Return To Zero Protocols

This work scrutinizes the implementation and performance analysis of novel self-timed asynchronous logic. These templates are based on a delay-insensitive (DI) logic paradigm known as NULL Convention Logic (NCL) that supports RTZ protocol, includes clock-free operation, dual-rail encoding and monotonic transitions. Potential benefits include inherent robustness, low power, reduced noise ratio, easy design reuse and reduced switching activity. In this work quantitative analysis have been carried out on both conventional static CMOS approach and the proposed static NCL approach using Tanner tools and the corresponding power, delay, noise and power-delay product for both designs have been collected and compared.